The present invention relates generally to low dropout (LDO) voltage regulators which have stable operation and high phase margin over wide ranges of output capacitance and effective-series-resistance.
Referring to FIG. 1A, an NMOS LDO regulator 1A includes an error amplifier 2 having its (+) input coupled to receive a reference voltage Vref and its output voltage Vg coupled by conductor 3 to the gate of an N-channel pass transistor 4, the drain of which receives the input voltage Vin which is to be regulated. The source of pass transistor 4 produces a regulated output voltage Vout that is coupled by an output conductor 5 to a load capacitor 11 of capacitance CL to a load IL represented by a current source 7 and to the first terminal of a resistor 9. The second terminal of resistor 9 is connected by a feedback conductor 6 to a first terminal of a second resistor 10 having its second terminal connected to ground. Resistors 9 and 10 form a voltage divider, from which a feedback signal on conductor 6 is applied to the (−) input of error amplifier 2.
The transconductance gmi of error amplifier 2 in FIG. 1A and the gate capacitance Cg of pass transistor 4 set the bandwidth of the loop to be equal to gmi/Cg. NMOS LDO regulators as shown in FIG. 1A generally do not need a load capacitor for stability. Load capacitors nevertheless are used in most applications to help improve transient performance of the LDO regulator, as capacitors can supply instantaneous current in the event of a load transient. Due to the finite transconductance gmo of pass transistor 4, the load capacitance CL causes a second pole at the frequency gmo/CL (in radians). For a given output capacitor CL, the second pole can be considered to “slide” upward along the −20 dB/decade line 30-2 as indicated in the Bode plot of FIG. 3 when the load current IL decreases. This causes a decrease of the phase margin of LDO regulator 1A as the second pole moves away from the 0 dB line 34 and may result in circuit instability.
Therefore, it usually is recommended that high ESR (effective-series-resistance) output capacitors, such as tantalum capacitors, be used for NMOS LDO regulators in order to provide a “zero” to cancel the second pole. However, the use of high ESR tantalum output capacitors compromises the transient performance of the LDO regulator and also may result in capacitor reliability problems because of joule heating effects of the ES are caused by the transient current.
As progress continues to be made in reducing the size and cost of ceramic capacitors, it is very important for an integrated circuit LDO regulator to be stable when used with a low ES are ceramic output capacitor in order to achieve a good level of success in the market.
FIG. 1B shows another NMOS LDO voltage regulator topology which has been attempted to solve the instability problem in the assignee's TPS731 product, wherein the signal Vg on the gates of the N-channel transistor 14 and the N-channel pass transistor 4 is coupled to the source of transistor 14 and then is AC-coupled by feedback capacitor Cf and conductor 6A to the (−) input of the error amplifier 2. Transistor 14 provides another feedback path in which the signal is not affected by the load capacitance CL. However, this topology was not implemented in the above mentioned TPS731 product for two reasons. First, the topology was found to be impractical because Cf and Rf need to be large and therefore require too much die area for the signal path to be effective. Second, Rf can not be too large because that would result in too much noise. Nevertheless, the idea of a parallel AC-coupled feedback path is very valuable for LDO loop compensation design.
There is an unmet need for an integrated circuit LDO voltage regulator which can be used with a load capacitor of low effective-series-resistance (ESR) having improved stable operation and high phase margin compared to the prior art, in order to avoid reliability problems due to joule heating effects caused by transient current in the load capacitor.